Inverter cell for a ring oscillator

ABSTRACT

An inverter cell for a ring oscillator. The inverter cell includes a first transistor, a second transistor, a first resistor, a second resistor, and a capacitor. A voltage input terminal is connected to gates of the first transistor and the second transistor. A voltage output terminal is connected drains of the first transistor and the second transistor. The first resistor is connected to the source of the first transistor and a first voltage potential. The second resistor is connected to the source of the second transistor and a second voltage potential. The capacitor has a first end directly connected to the source of the first transistor and the first end of the first resistor and a second end directly connected to the source of the second transistor and the first end of the second resistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is a continuation of U.S. patent application Ser. No. 13/212,771 (now U.S. Pat. No. 8,624,681), filed on Aug. 18, 2011, which claims the benefit of U.S. Provisional Application No. 61/376,391, filed on Aug. 24, 2010. The entire disclosures of the applications referenced above are incorporated herein by reference.

BACKGROUND

The present invention relates to oscillator circuits and in particular to a low noise CMOS ring oscillator.

Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

Complimentary Metal Oxide Semiconductor (CMOS) ring oscillators are widely used in Phase Locked Loop (PLL) circuits. PLLs are commonly used for clock and data recovery, frequency synthesis, clock generation circuitry, etc. Among the various types of CMOS ring oscillators, inverter based single ended or differential ring oscillators are recognized as being efficient and are often the ring oscillator design of choice.

FIG. 1 shows a schematic diagram for a three-stage inverter-based ring oscillator 100. The ring oscillator 100 comprises a chain of three inverters 102 a, 102 b, and 102 c connected in cascade fashion. The output of last inverter 102 c feeds back into the input of the first inverter 102 a. Inverter-based ring oscillators can be constructed with any odd number of inverters.

FIG. 1A is a circuit diagram of a typical inverter cell 102 that may be used for inverters 102 a, 102 b, and 102 c in the ring oscillator 100 shown in FIG. 1. The inverter cell 102 comprises a first transistor 122 and a second transistor 124. The transistors 122 and 124 may be Field Effect Transistors (FETs). A gate G of each transistor 122 and 124 is connected to an input terminal V_(in) of the inverter cell 112. A drain D of each transistor 122 and 124 is connected to an output terminal V_(OUT) of the inverter cell 102. A source S of transistor 122 is configured for connection to a first voltage potential; e.g., V_(SS). A source S of transistor 124 is configured for connection to a second voltage potential; e.g., V_(DD).

As semiconductor manufacturing processes continue to shrink and the requirements for higher switching speeds continue to increase, inverter-based ring oscillators are designed with increasingly smaller device sizes in order to maintain reasonable levels of power consumption. As device dimensions decrease, device noise in ring oscillators become significant. One kind of noise called “flicker noise,” which occurs in most electronic devices, is dominant at low frequencies. For inverter-based ring oscillator devices using deep submicron processes like 45 nm processes or 30 nm processes, flicker noise can predominate at frequencies as high as about 10 MHz-20 MHz. For frequencies above a corner frequency of 10 MHz to 20 MHz, “thermal noise” tends to predominate. For circuit applications that run at 1 MHz to 10 MHz, the flicker noise is the predominant noise source, and can manifest itself in the output signal of the ring oscillator as phase noise (frequency domain) or jitter (time domain).

SUMMARY

In accordance with disclosed embodiments, a ring oscillator includes a number of inverter cells connected in cascade fashion. An output of each inverter cell is connected to an input of another inverter cell. Each inverter cell includes first and second resistors for connection to respective first and second voltage potentials. An output of the ring oscillator is an oscillatory signal having a frequency that is based at least on the resistance values of the first and second resistors.

In some embodiments, each inverter cell includes first and second transistors. Sources of the first and second transistors are connected to the first and second resistors, respectively.

In some embodiments, each inverter cell further includes a capacitor connected to the first and second transistors.

In an embodiment, a phase locked loop comprises a ring oscillator in accordance with the present disclosure. In another embodiment, a frequency divider circuit comprises a ring oscillator in accordance with the present disclosure.

The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a ring oscillator.

FIG. 1A shows details for an inverter cell.

FIGS. 2 and 2A shows details for inverter cells in accordance with the present disclosure.

FIGS. 3, 3A, and 3B illustrate embodiments of ring oscillators in accordance with the principles of the present invention.

FIGS. 4 and 4A illustrate embodiments of crystal oscillators in accordance with the principles of the present invention.

FIG. 5 is a block diagram of a phase locked loop in accordance with the present disclosure.

FIG. 6, is a block diagram of a frequency divider circuit in accordance with the present disclosure.

DESCRIPTION

In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

Referring to FIG. 2, an inverter cell 202 in accordance with embodiments of the present disclosure comprises a first transistor M₁ and a second transistor M₂, and a first resistor R₁ and a second resistor R₂. The transistors M₁ and M₂ may be FETs; e.g., Metal Oxide Semiconductor FETs (MOSFETs). In an embodiment, the transistor M₁ is an N-channel MOSFET and the transistor M₂ is a P-channel MOSFET. It will be appreciated of course that other combinations of transistor types for M₁ and M₂ may be employed.

An input terminal V_(in) of the inverter cell 202 is connected to a gate G of each transistor M₁ and M₂. An output terminal V_(OUT) of the inverter cell 202 is connected to a drain D of each transistor M₁ and M₂. A source S of transistor M₁ is connected to a first terminal 212 of resistor R₁. A second terminal 214 of resistor R₁ may be connected to a first power rail 222 that is configured for connection to a first voltage potential; e.g., V_(SS). A source S of transistor M₂ is connected to a first terminal 216 of resistor R₂. A second terminal 218 of resistor R₂ may be connected to a second power rail 224 that is configured for connection to a second voltage potential; e.g., V_(DD).

FIG. 3 illustrates an embodiment of a ring oscillator 300 comprising inverter cells 302 a, 302 b, and 302 c of the form shown in FIG. 2. In some embodiments, the inverter cells 302 a, 302 b, and 302 c are connected in cascade fashion. Accordingly, the output V_(OUT) of cell 302 a is fed into the input V_(in) of cell 302 b. The output V_(OUT) of cell 302 b is fed into the input V_(in) of cell 302 c. The output V_(OUT) of cell 302 c is fed back into the input V_(in) of cell 302 a. The resistors R₁ and R₂ of each cell 302 a, 302 b, and 302 c may be connected to respective power rails 322 and 324 to provide power to the ring oscillator 300. The power rails 322 and 324, in turn, may be at respective first and second voltage potentials (e.g., V_(SS) and V_(DD)). In some embodiments, the ring oscillator 300 may include additional cells. For example, FIG. 3A illustrates a more generic ring oscillator design 300′ comprising some number of stages 302 a through 302 n other than the three stages shown in FIG. 3. The number of stages 302 a through 302 n may be an even number or an odd number.

The ring oscillator 300 shown in FIG. 3 may output an oscillatory signal 304 a at a terminal 304. The resistors R₁ and R₂ can attenuate the level of flicker noise (phase noise) in the output signal 304 a as a result of the effect of resistor degeneration. Though the output signal 304 a is oscillatory, its shape may not be adequate for use by electronic circuits that the ring oscillator 300 is being used in. For example, the output signal 304 a may not be a properly formed square (or rectangular) wave or a properly formed sinusoidal wave. Accordingly, additional circuitry may be used to produce a suitable waveform. For instance, the output signal 304 a may be further processed by a buffer that can output a properly formed square wave based on the received output signal.

Referring back to FIGS. 1 and 1A, the frequency of the output signal of the ring oscillator 100 is dependent upon various aspects of the design of the ring oscillator. For example, the number of inverter stages that comprise the ring oscillator 100 affects the frequency. The frequency will decrease as the number of inverter stages increase, because each additional inverter adds to the propagation delay of the signal along the chain of inverters and hence how frequently the output signal will switch between HI and LO logic levels.

The transconductance (g_(m)) of the inverters that comprise a ring oscillator 100 is another factor that affects the frequency of the output signal of the ring oscillator. The transconductance of a CMOS inverter is a function of the device size of its constituent transistors. Referring to the inverter cell 102 shown in FIG. 1A, for example, the device size of FET transistor 124 is typically specified by its channel dimensions, which may be expressed as the ratio W/L, where W is the FET channel width (W) and L is the FET channel length. FIG. 1A shows typical channel dimensions for the FET transistors 122 and 124 of the inverter 102. For example, transistor 122 may have a channel dimension of 600/100 and transistor 124 may have a channel dimension of 1200/100. The transconductance also affects power consumption in each inverter during operation, and hence power consumption of the ring oscillator 100 as a whole.

Referring now to FIGS. 2 and 3, in accordance with embodiments of the present disclosure, the transconductance of the inverter 202 shown in FIG. 2 is dependent not only on the channel dimensions of FET transistors M₁ and M₂, but also on the sizes of the resistors R₁ and R₂. Suppose the inverters 302 a, 302 b, and 302 c comprising ring oscillator 300 are designed to have substantially the same transconductance as the design of inverter 102 shown in FIG. 1A. For example, the transconductance of the particular inverter design shown in FIG. 2 is substantially the same as the transconductance as the design of inverter 102 shown in FIG. 1A, where the channel dimension of FET transistor M₁ is 1200/50, the channel dimension of FET transistor M₂ is 2400/50, and each resistor R₁ and R₂ is 600Ω. In other embodiments, the resistors R₁ and R₂ may have different resistance values. Suppose the inverters 302 a, 302 b, and 302 c use the inverter design of FIG. 2. Since the ring oscillator 300 is also a three-stage device as is ring oscillator 100, then the output frequency and power consumption performance of both ring oscillators 100 and 300 are about the same. However, the ring oscillator 300 will exhibit attenuated flicker noise, and in particular reduced phase noise.

Simulations of a three-stage ring oscillator designed using the inverter cell 102 of FIG. 1A and a three-stage ring oscillator designed using the inverter cell 202 of FIG. 2 were compared. Both ring oscillators were designed to produce an output signal in the gigahertz range. The simulations have shown that the ring oscillator based on the inverter cell 202 exhibits a 2.5 dB reduction in phase noise at 10 MHz as compared to the ring oscillator based on the inverter cell 102. Simulations were made using ring oscillators designed for 3-5 GHz output signals with even greater improvement; a 6 dB difference in phase noise was noted.

In some embodiments, the resistor degeneration effect in the ring oscillator 300 can be increased to further attenuate phase noise by increasing the sizes of the resistors R₁ and R₂ in the ring oscillator. However, the frequency of the output signal 304 a is inversely related to the resistance of the resistors R₁ and R₂. Therefore, increasing the resistance of resistors R₁ and R₂ in an attempt to further attenuate phase noise will also decrease the frequency of the output signal 304 a.

FIG. 2A shows an embodiment of an inverter cell 212 that is a variation of the inverter cell 202 shown in FIG. 2, wherein each resistor R₁ and R₂ is designed for 1 KΩ to provide additional phase noise attenuation. The inverter cell 212 includes a capacitor C to compensate for the reduction in the frequency of the output signal 304 a that may result from using bigger resistors R₁ and R₂. In the particular embodiment shown in FIG. 2A, the capacitor C has a capacitance of 10 pF.

FIG. 3B shows an embodiment of a ring oscillator 310 comprising inverter cells 312 a, 312 b, and 312 c of the form shown in FIG. 2A. The cells 312 a, 312 b, and 312 c are connected in cascade fashion; for example, the output V_(OUT) of cell 312 a is fed into the input V_(in) of cell 312 b. The output V_(OUT) of cell 312 b is fed into the input V_(in) of cell 312 c. The output V_(OUT) of cell 312 c is fed back into the input V_(in) of cell 312 a. In some embodiments, the ring oscillator 310 may include additional cells. Simulations of this embodiment of the ring oscillator have shown an additional 1 dB improvement in the reducing phase noise.

In other embodiments, the inverter cell 202 of FIG. 2 may be used in a crystal oscillator design. The inverter cell 202 itself exhibits improved flicker noise performance because of the effect of resistor degeneration provided by resistors R₁ and R₂. Accordingly, a crystal-based oscillator design that employs the inverter cell 202 may likewise exhibit a similar improvement in reduced flicker noise.

FIG. 4 illustrates a crystal oscillator 400 in accordance with embodiments of the present disclosure. The oscillator 400 comprises a suitable crystal 406. A pi (π) network comprising capacitors C1 and C2 may be used to set a resonant frequency in the crystal 406. An inverter 402 of the form illustrated in FIG. 2 is connected in parallel with the crystal. A resistor R is connected in parallel with the inverter 402 and serves to bias the inverter 402 to operate within its linear region. An output terminal 404 of the oscillator 400 may be provided in order to output an oscillatory signal that is generated by the oscillator. In other embodiments, an oscillator 410 shown in FIG. 4A may include an inverter 412 of the form illustrated in FIG. 2A to attain greater flicker noise attenuation, while maintaining a suitable output frequency.

In some embodiments, the ring oscillator 300 in FIG. 3 may be designed for operation in the gigahertz range. The ring oscillator 300 in FIG. 3 may be used in a PLL designed for operation in the range of 10 MHz±5 MHz. In some embodiments, the ring oscillator 300 in FIG. 3 may be designed for operation at a corner frequency F_(c) between the region of flicker noise dominance and thermal noise dominance.

As illustrated in FIG. 5, disclosed embodiments of a ring oscillator in accordance with principles of the present invention may be embodied in a PLL circuit 500. A phase detector 502 receives two inputs: a reference input F_(ref) and feedback from an output F_(out) of a Voltage Controlled Oscillator (VCO) 506. Circuitry for the phase detector 502 is well known. The VCO 506 comprises an embodiment of a ring oscillator in accordance with principles of the present invention. In some embodiments, the VCO 506 comprises an embodiment of a crystal oscillator in accordance with principles of the present invention. The output of the phase detector 502 is fed to the VCO 506 via filter 504. The output of the phase detector 502 controls the VCO 506 such that the phase difference between the two inputs F_(ref) and F_(out) is held constant. The filter 504 determines the dynamics of the PLL circuit 500, such as how quickly the PLL circuit 500 responds to changes in the output of the VCO 506.

As illustrated in FIG. 6, a ring oscillator in accordance with principles of the present invention may be embodied in a frequency synthesizer circuit 600. A frequency synthesizer may be based on a PLL circuit, for example such as the one depicted in FIG. 5. Accordingly, a phase detector 602 receives two inputs: a reference input F_(ref) and feedback based on an output F_(out) of a VCO 606. The VCO 606 comprises an embodiment of a ring oscillator in accordance with principles of the present invention. In some embodiments, the VCO 606 comprises an embodiment of a crystal oscillator in accordance with principles of the present invention. A programmable divide-by-n network 608 receives two inputs: the output F_(out) from the VCO 606 and a counter N, and outputs a signal

$F_{out}^{\prime}\left( {= \frac{F_{out}}{N}} \right)$ that feeds into the phase detector 602. The output of the phase detector 602 is fed to the VCO 606 via filter 604. The output of the phase detector 602 controls the VCO 606 such that the phase difference between the two inputs F_(ref) and F_(out)′ is held constant. The filter 604 determines the dynamics of the PLL circuit 600, such as how quickly the PLL circuit 600 responds to changes in the output of the VCO 606.

As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims. 

What is claimed is:
 1. An inverter cell for a ring oscillator, the inverter cell comprising: a first transistor having a source, a drain, and a gate; a second transistor having a source, a drain, and a gate, wherein a voltage input terminal is connected to each of (i) the gate of the first transistor and (ii) the gate of the second transistor, and a voltage output terminal is connected to each of (i) the drain of the first transistor and (ii) the drain of the second transistor; a first resistor having (i) a first end connected to the source of the first transistor and (ii) a second end connected to a first voltage potential; a second resistor having (i) a first end connected to the source of the second transistor and (ii) a second end connected to a second voltage potential that is different than the first voltage potential; and a capacitor having (i) a first end directly connected to the source of the first transistor and the first end of the first resistor and (ii) a second end directly connected to the source of the second transistor and the first end of the second resistor.
 2. The inverter cell of claim 1, wherein the capacitor is connected (i) in parallel with the first transistor and the second transistor and (ii) in series with the first resistor and the second resistor.
 3. The inverter cell of claim 1, wherein the first transistor, the second transistor, the first resistor, and the second resistor are connected in series.
 4. The inverter cell of claim 1, wherein a flicker noise of the ring oscillator corresponds to a resistance value of the first resistor and a resistance value of the second resistor.
 5. The inverter cell of claim 1, wherein the voltage output terminal is configured to output an oscillatory signal.
 6. The inverter cell of claim 5, wherein the capacitor is configured to increase a frequency of the oscillatory signal.
 7. A ring oscillator comprising a plurality of the inverter cells of claim
 1. 8. The ring oscillator of claim 7, wherein the inverter cells are connected in a cascade arrangement.
 9. The ring oscillator of claim 7, wherein an output of each of the inverter cells is connected to an input of another of the inverter cells.
 10. A crystal oscillator comprising the inverter cell of claim
 1. 11. A ring oscillator, comprising: a plurality of inverter cells, each of the inverter cells comprising: a first transistor having a source, a drain, and a gate; a second transistor having a source, a drain, and a gate, wherein a voltage input terminal is connected to each of (i) the gate of the first transistor and (ii) the gate of the second transistor, and a voltage output terminal is connected to each of (i) the drain of the first transistor and (ii) the drain of the second transistor; a first resistor having (i) a first end connected to the source of the first transistor and (ii) a second end connected to a first voltage potential; a second resistor having (i) a first end connected to the source of the second transistor and (ii) a second end connected to a second voltage potential that is different than the first voltage potential; and a capacitor having (i) a first end directly connected to the source of the first transistor and the first end of the first resistor and (ii) a second end directly connected to the source of the second transistor and the first end of the second resistor.
 12. The ring oscillator of claim 11, wherein the inverter cells are connected in a cascade arrangement.
 13. The ring oscillator of claim 11, wherein an output of each of the inverter cells is connected to an input of another of the inverter cells.
 14. The ring oscillator of claim 11, wherein the capacitor is connected (i) in parallel with the first transistor and the second transistor and (ii) in series with the first resistor and the second resistor.
 15. The ring oscillator of claim 11, wherein the first transistor, the second transistor, the first resistor, and the second resistor are connected in series.
 16. The ring oscillator of claim 11, wherein a flicker noise of the ring oscillator corresponds to a resistance value of the first resistor and a resistance value of the second resistor.
 17. The ring oscillator of claim 11, wherein the voltage output terminal is configured to output an oscillatory signal.
 18. The ring oscillator of claim 17, wherein the capacitor is configured to increase a frequency of the oscillatory signal. 